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r february 11, 2000 (version 1.8) 6-101 xc4000e and xc4000x series field programmable gate arrays 6 xc4000e electrical speci?cations de?nition of terms in the following tables, some speci?cations may be designated as advance or preliminary. these terms are de?ned as follows: advance: initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. values are subject to change. use as estimates, not for production. preliminary: based on preliminary characterization. further changes are not expected. unmarked: speci?cations not identi?ed as either advance or preliminary are to be considered final. except for pin-to-pin input and output parameters, the a.c. parameter delay speci?cations included in this document are derived from measuring internal test patterns. all speci?cations are representative of worst-case supply voltage and junction temperature conditions. all speci?cations subject to change without notice. xc4000e dc characteristics absolute maximum ratings recommended operating conditions symbol description value units v cc supply voltage relative to gnd -0.5 to +7.0 v v in input voltage relative to gnd (note 1) -0.5 to v cc +0.5 v v ts voltage applied to 3-state output (note 1) -0.5 to v cc +0.5 v t stg storage temperature (ambient) -65 to +150 c t sol maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 c t j junction temperature ceramic packages +150 c plastic packages +125 c note 1: maximum dc excursion above v cc or below ground must be limited to either 0.5 v or 10 ma, whichever is easier to achieve. during transitions, the device pins may undershoot to -2.0 v or overshoot to v cc + 2.0 v, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 ma. note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under recommended operating conditions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. symbol description min max units v cc supply voltage relative to gnd, t j = -0 c to +85 c commercial 4.75 5.25 v supply voltage relative to gnd, t j = -40 c to +100 c industrial 4.5 5.5 v supply voltage relative to gnd, t c = -55 c to +125 c military 4.5 5.5 v v ih high-level input voltage ttl inputs 2.0 v cc v cmos inputs 70% 100% v cc v il low-level input voltage ttl inputs 0 0.8 v cmos inputs 0 20% v cc t in input signal transition time 250 ns notes: at junction temperatures above those listed above, all delay parameters increase by 0.35% per c. input and output measurement thresholds for ttl are 1.5 v and for cmos are 2.5 v.
r xc4000e and xc4000x series field programmable gate arrays 6-102 february 11, 2000 (version 1.8) dc characteristics over operating conditions symbol description min max units v oh high-level output voltage @ i oh = -4.0ma, v cc min ttl outputs 2.4 v high-level output voltage @ i oh = -1.0ma, v cc min cmos outputs v cc -0.5 v v ol low-level output voltage @ i ol = 12.0ma, v cc min (note 1) ttl outputs 0.4 v cmos outputs 0.4 v i cco quiescent fpga supply current (note 2) commercial 3.0 ma industrial 6.0 ma military 6.0 ma i l input or output leakage current -10 +10 m a c in input capacitance (sample tested) pqfp and mqfp packages 10 pf other packages 16 pf i rin* pad pull-up (when selected) @ v in = 0v (sample tested) -0.02 -0.25 ma i rll* horizontal longline pull-up (when selected) @ logic low 0.2 2.5 ma notes: with 50% of the outputs simultaneously sinking 12ma, up to a maximum of 64 pins. with no output current loads, no active input or longline pull-up resistors, all package pins at vcc or gnd, and the fpga con?gured with a development system tie option. *characterized only.
r february 11, 2000 (version 1.8) 6-103 xc4000e and xc4000x series field programmable gate arrays 6 xc4000e switching characteristics testing of the switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb ?ip-?ops are clocked by the global clock net. when fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. for more speci?c, more precise, and worst-case guaranteed data, re?ecting the actual routing structure, use the values provided by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature). global buffer switching characteristic guidelines speed grade -4 -3 -2 -1 units description symbol device max max max max from pad through primary buffer, to any clock k t pg xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 7.0 7.0 7.5 8.0 11.0 11.5 12.0 12.5 4.7 4.7 5.3 6.1 6.3 6.8 7.0 7.2 4.0 4.3 5.2 5.2 5.4 5.8 6.4 6.9 3.5 3.8 4.6 4.6 4.8 5.2 6.0 C ns ns ns ns ns ns ns ns from pad through secondary buffer, to any clock k t sg xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 7.5 7.5 8.0 8.5 11.5 12.0 12.5 13.0 5.2 5.2 5.8 6.6 6.8 7.3 7.5 7.7 4.4 4.7 5.6 5.6 5.8 6.2 6.7 7.2 4.0 4.3 5.1 5.1 5.3 5.7 6.5 C ns ns ns ns ns ns ns ns
r xc4000e and xc4000x series field programmable gate arrays 6-104 february 11, 2000 (version 1.8) horizontal longline switching characteristic guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more speci?c, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature). values apply to all xc4000e devices unless otherwise noted. the following guidelines re?ect worst-case values over the recommended operating conditions. speed grade -4 -3 -2 -1 units description symbol device max max max max tbuf driving a horizontal longline (ll): i going high or low to ll going high or low, while t is low. buffer is constantly active. (note1) t io1 xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 5.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 4.2 5.0 5.9 6.3 6.4 7.2 8.2 9.1 3.4 4.0 4.7 5.0 5.1 5.7 7.3 7.3 2.9 3.4 4.0 4.3 4.4 4.9 5.6 C ns ns ns ns ns ns ns ns i going low to ll going from resistive pull-up high to active low. tbuf configured as open-drain. (note1) t io2 xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 5.0 6.0 7.8 8.1 10.5 11.0 12.0 12.0 4.2 5.3 6.4 6.8 6.9 7.7 8.7 9.6 3.6 4.5 5.4 5.8 5.9 6.5 8.7 9.6 3.1 3.8 4.6 4.9 5.0 5.5 7.4 C ns ns ns ns ns ns ns ns t going low to ll going from resistive pull-up or floating high to active low. tbuf configured as open-drain or active buffer with i = low. (note1) t on xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 5.5 7.0 7.5 8.0 8.5 8.7 11.0 11.0 4.6 6.0 6.7 7.1 7.3 7.5 8.4 8.4 3.9 5.7 5.7 6.0 6.2 7.0 7.1 7.1 3.5 4.7 4.9 5.2 5.4 6.2 6.3 C ns ns ns ns ns ns ns ns t going high to tbuf going inactive, not driving ll t off all devices 1.8 1.5 1.3 1.1 ns t going high to ll going from low to high, pulled up by a single resistor. (note 1) t pus xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 20.0 23.0 25.0 27.0 29.0 32.0 35.0 42.0 14.0 16.0 18.0 20.0 22.0 26.0 32.5 39.1 14.0 16.0 18.0 20.0 22.0 26.0 32.5 39.1 12.0 14.0 16.0 16.0 18.0 21.0 26.0 C ns ns ns ns ns ns ns ns t going high to ll going from low to high, pulled up by two resistors. (note1) t puf xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 9.0 10.0 11.5 12.5 13.5 15.0 16.0 18.0 7.0 8.0 9.0 10.0 11.0 13.0 14.8 16.5 6.0 6.8 7.7 8.5 9.4 11.7 14.8 16.5 5.4 5.8 6.5 7.5 8.0 9.4 10.5 C ns ns ns ns ns ns ns ns note 1: these values include a minimum load. use the static timing analyzer to determine the delay for each destination.
r february 11, 2000 (version 1.8) 6-105 xc4000e and xc4000x series field programmable gate arrays 6 wide decoder switching characteristic guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more speci?c, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature). values apply to all xc4000e devices unless otherwise noted. the following guidelines re?ect worst-case values over the recommended operating conditions. speed grade -4 -3 -2 -1 units description symbol device max max max max full length, both pull-ups, inputs from iob i-pins t waf xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 9.2 9.5 12.0 12.5 15.0 16.0 17.0 18.0 5.0 6.0 7.0 8.0 9.0 11.0 13.9 16.9 5.0 6.0 7.0 8.0 9.0 11.0 13.9 16.9 4.3 5.1 6.0 6.5 7.5 8.6 10.1 C ns ns ns ns ns ns ns ns full length, both pull-ups, inputs from internal logic t wafl xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 12.0 12.5 14.0 16.0 18.0 19.0 20.0 21.0 7.0 8.0 9.0 10.0 11.0 13.0 15.5 18.9 7.0 8.0 9.0 10.0 11.0 13.0 15.5 18.9 5.5 6.4 7.0 7.5 8.5 10.0 11.8 C ns ns ns ns ns ns ns ns half length, one pull-up, inputs from iob i-pins t wao xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 10.5 10.5 13.5 14.0 16.0 17.0 18.0 19.0 6.0 7.0 8.0 9.0 10.0 12.0 15.0 17.6 6.0 7.0 8.0 9.0 10.0 12.0 15.0 17.6 5.1 6.0 6.5 7.0 7.5 10.0 11.8 C ns ns ns ns ns ns ns ns half length, one pull-up, inputs from internal logic t waol xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 12.0 12.5 14.0 16.0 18.0 19.0 20.0 21.0 8.0 9.0 10.0 11.0 12.0 14.0 16.8 19.6 8.0 9.0 10.0 11.0 12.0 14.0 16.8 19.6 6.0 7.0 7.6 8.4 9.2 10.8 12.6 C ns ns ns ns ns ns ns ns note 1: these delays are speci?ed from the decoder input to the decoder output. note 2: fewer than the speci?ed number of pullup resistors can be used, if desired. using fewer pullups reduces power consumption but increases delays. use the static timing analyzer to determine delays if fewer pullups are used.
r xc4000e and xc4000x series field programmable gate arrays 6-106 february 11, 2000 (version 1.8) xc4000e clb characteristics guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more speci?c, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature). values apply to all xc4000e devices unless otherwise noted clb switching characteristics guidelines speed grade -4 -3 -2 -1 units description symbol min max min max min max min max combinatorial delays f/g inputs to x/y outputs f/g inputs via h to x/y outputs c inputs via sr through h to x/y outputs c inputs via h to x/y outputs c inputs via din through h to x/y outputs t ilo t iho t hh0o t hh1o t hh2o 2.7 4.7 4.1 3.7 4.5 2.0 4.3 3.3 3.6 3.6 1.6 2.7 2.4 2.2 2.6 1.3 2.2 1.9 1.6 1.9 ns ns ns ns ns clb fast carry logic operand inputs (f1, f2, g1, g4) to cout add/subtract input (f3) to cout initialization inputs (f1, f3) to cout cin through function generators to x/y outputs cin to cout, bypass function generators t opcy t ascy t incy t sum t byp 3.2 5.5 1.7 3.8 1.0 2.6 4.4 1.7 3.3 0.7 2.1 3.7 1.4 2.6 0.6 1.7 2.5 1.2 1.8 0.5 ns ns ns ns ns sequential delays clock k to outputs q t cko 3.7 2.8 2.8 1.9 ns setup time before clock k f/g inputs f/g inputs via h c inputs via h0 through h c inputs via h1 through h c inputs via h2 through h c inputs via din c inputs via ec c inputs via s/r, going low (inactive) c in input via f/g c in input via f/g and h t ick t ihck t hh0ck t hh1ck t hh2ck t dick t ecck t rck t cck t chck 4.0 6.1 4.5 5.0 4.8 3.0 4.0 4.2 2.5 4.2 3.0 4.6 3.6 4.1 3.8 2.4 3.0 4.0 2.1 3.5 2.4 3.9 3.5 3.3 3.7 2.0 2.6 4.0 1.8 2.8 2.4 2.1 2.5 1.0 2.0 1.5 ns ns ns ns ns ns ns ns ns ns
r february 11, 2000 (version 1.8) 6-107 xc4000e and xc4000x series field programmable gate arrays 6 xc4000e clb characteristics guidelines (continued) speed grade -4 -3 -2 -1 units description symbol min max min max min max min max hold time after clock k f/g inputs f/g inputs via h c inputs via h0 through h c inputs via h1 through h c inputs via h2 through h c inputs via din c inputs via ec c inputs via sr, going low (inactive) t cki t ckih t ckhh0 t ckhh1 t ckhh2 t ckdi t ckec t ckr 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ns ns ns ns ns ns ns ns clock clock high time clock low time t ch t cl 4.5 4.5 4.0 4.0 4.0 4.0 3.0 3.0 ns ns set/reset direct width (high) delay from c inputs via s/r, going high to q t rpw t rio 5.5 6.5 4.0 4.0 4.0 4.0 3.0 3.0 ns ns master set/reset (note 1) width (high or low) delay from global set/reset net to q global set/reset inactive to first active clock k edge t mrw t mrq t mrk 13.0 23.0 11.5 18.7 11.5 17.4 10.0 15.0 ns ns toggle frequency (note 2) f tog 111 125 125 166 mhz note 1: timing is based on the xc4005e. for other devices see the static timing analyzer. note 2: export control max. ?ip-?op toggle rate.
r xc4000e and xc4000x series field programmable gate arrays 6-108 february 11, 2000 (version 1.8) clb edge-triggered (synchronous) ram switching characteristic guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more speci?c, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature). values apply to all xc4000e devices unless otherwise noted. single port ram speed grade -4 -3 -2 -1 units size symbol min max min max min max min max write operation address write cycle time (clock k period) 16x2 32x1 t wcs t wcts 15.0 15.0 14.4 14.4 11.6 11.6 8.0 8.0 ns ns clock k pulse width (active edge) 16x2 32x1 t wps t wpts 7.5 7.5 1ms 1ms 7.2 7.2 1ms 1ms 5.8 5.8 1ms 1ms 4.0 4.0 ns ns address setup time before clock k 16x2 32x1 t ass t asts 2.8 2.8 2.4 2.4 2.0 2.0 1.5 1.5 ns ns address hold time after clock k 16x2 32x1 t ahs t ahts 0 0 0 0 0 0 0 0 ns ns din setup time before clock k 16x2 32x1 t dss t dsts 3.5 2.5 3.2 1.9 2.7 1.7 1.5 1.5 ns ns din hold time after clock k 16x2 32x1 t dhs t dhts 0 0 0 0 0 0 0 0 ns ns we setup time before clock k 16x2 32x1 t wss t wsts 2.2 2.2 2.0 2.0 1.6 1.6 1.5 1.5 ns ns we hold time after clock k 16x2 32x1 t whs t whts 0 0 0 0 0 0 0 0 ns ns data valid after clock k 16x2 32x1 t wos t wots 10.3 11.6 8.8 10.3 7.9 9.3 6.5 7.0 ns ns note 1: timing for the 16x1 ram option is identical to 16x2 ram timing. note 2: applicable read timing speci?cations are identical to level-sensitive read timing. dual-port ram speed grade -4 -3 -2 -1 units size symbol min max min max min max min max write operation address write cycle time (clock k period) clock k pulse width (active edge) address setup time before clock k address hold time after clock k din setup time before clock k din hold time after clock k we setup time before clock k we hold time after clock k data valid after clock k 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 t wcds t wpds t asds t ahds t dsds t dhds t wsds t whds t wods 15.0 7.5 2.8 0 2.2 0 2.2 0.3 1 ms 10.0 14.4 7.2 2.5 0 2.5 0 1.8 0 1 ms 7.8 11.6 5.8 2.1 0 1.6 0 1.6 0 1ms 7.0 8.0 4.0 1.5 0 1.5 0 1.5 0 6.5 ns ns ns ns ns ns ns ns ns note: applicable read timing speci?cations are identical to level-sensitive read timing
r february 11, 2000 (version 1.8) 6-109 xc4000e and xc4000x series field programmable gate arrays 6 clb ram synchronous (edge-triggered) write timing waveforms x6461 wclk (k) we address data in data out old new t dss t dhs t ass t ahs t wss t wps t whs t wos t ilo t ilo wclk (k) we address data in t dsds t dhds t asds t ahds t wsds t wpds t whds x6474 data out old new t wods t ilo t ilo single port dual port
r xc4000e and xc4000x series field programmable gate arrays 6-110 february 11, 2000 (version 1.8) clb level-sensitive ram switching characteristic guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more speci?c, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature). values apply to all xc4000e devices unless otherwise noted. speed grade -4 -3 -2 -1 units description size symbol min max min max min max min max write operation address write cycle time 16x2 32x1 t wc t wct 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 ns ns write enable pulse width (high) 16x2 32x1 t wp t wpt 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 ns ns address setup time before we 16x2 32x1 t as t ast 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 ns ns address hold time after end of we 16x2 32x1 t ah t aht 2.5 2.0 2.0 2.0 2.0 2.0 2.0 2.0 ns ns din setup time before end of we 16x2 32x1 t ds t dst 4.0 5.0 2.2 2.2 0.8 0.8 0.8 0.8 ns ns din hold time after end of we 16x2 32x1 t dh t dht 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 ns ns read operation address read cycle time 16x2 32x1 t rc t rct 4.5 6.5 3.1 5.5 2.6 3.8 2.6 3.8 ns ns data valid after address change (no write enable) 16x2 32x1 t ilo t iho 2.7 4.7 1.8 3.2 1.6 2.7 1.6 2.7 ns ns read operation, clocking data into flip-flop address setup time before clock k 16x2 32x1 t ick t ihck 4.0 6.1 3.0 4.6 2.4 3.9 2.4 3.9 ns ns read during write data valid after we goes active (din stable before we) 16x2 32x1 t wo t wot 10.0 12.0 6.0 7.3 4.9 5.6 4.9 5.6 ns ns data valid after din (din changes during we) 16x2 32x1 t do t dot 9.0 11.0 6.6 7.6 5.8 6.2 5.8 6.2 ns ns read during write, clocking data into flip-flop we setup time before clock k 16x2 32x1 t wck t wckt 8.0 9.6 6.0 6.8 5.1 5.8 5.1 5.8 ns ns data setup time before clock k 16x2 32x1 t dck t dckt 7.0 8.0 5.2 6.2 4.4 5.3 4.4 5.3 ns ns note 1: timing for the 16x1 ram option is identical to 16x2 ram timing.
r february 11, 2000 (version 1.8) 6-111 xc4000e and xc4000x series field programmable gate arrays 6 clb level-sensitive ram timing waveforms wc t ilo t cko t do t dh t wo t cko t wck t dck t ick t ch t wo t wp t valid valid (old) valid (old) valid (previous) valid (new) valid (new) valid address x,y outputs clock xq, yq outputs write enable x, y outputs x, y outputs xq, yq outputs write enable data in clock data in (stable during we) data in (changing during we) read without write read, clocking data into flip-flop read during write, clocking data into flip-flop read during write write enable data in write as t wp t ds t dh t required ah t wp t old new valid valid x2640
r xc4000e and xc4000x series field programmable gate arrays 6-112 february 11, 2000 (version 1.8) xc4000e guaranteed input and output parameters (pin-to-pin, ttl i/o) testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). listed below are representative values for typical pin locations and normal clock loading. for more speci?c, more precise, and worst-case guaranteed data, re?ecting the actual routing structure, use the values provided by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. values apply to all xc4000e devices unless otherwise noted. speed grade -4 -3 -2 -1 units description symbol device global clock to output (fast) using off t ickof (max) xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 12.5 14.0 14.5 15.0 16.0 16.5 17.0 17.0 10.2 10.7 10.7 10.8 10.9 11.0 11.0 12.6 8.7 9.1 9.1 9.2 9.3 9.4 10.2 10.8 5.8 6.2 6.4 6.6 6.8 7.2 7.4 C ns ns ns ns ns ns ns ns global clock to output (slew-limited) using off t icko (max) xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 16.5 18.0 18.5 19.0 20.0 20.5 21.0 21.0 14.0 14.7 14.7 14.8 14.9 15.0 15.1 15.3 11.5 12.0 12.0 12.1 12.2 12.8 12.8 13.0 7.8 8.2 8.4 8.6 8.8 9.2 9.4 C ns ns ns ns ns ns ns ns input setup time, using iff (no delay) t psuf (min) xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 2.5 2.0 1.9 1.4 1.0 0.5 0 0 2.3 1.2 1.0 0.6 0.2 0 0 0 2.3 1.2 1.0 0.6 0.2 0 0 0 1.5 0.8 0.6 0.2 0 0 0 C ns ns ns ns ns ns ns ns input hold time, using iff (no delay) t phf (min) xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 4.0 4.6 5.0 6.0 6.0 7.0 7.5 8.0 4.0 4.5 4.7 5.1 5.5 6.5 6.7 7.0 4.0 4.5 4.7 5.1 5.5 5.5 5.7 5.9 1.5 2.0 2.0 2.5 2.5 3.0 3.5 C ns ns ns ns ns ns ns ns input setup time, using iff (with delay) t psu (min) xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 8.5 8.5 8.5 8.5 8.5 8.5 9.5 9.5 7.0 7.0 7.0 7.0 7.0 7.0 7.0 7.6 6.0 6.0 6.0 6.0 6.0 6.0 6.8 6.8 5.0 5.0 5.0 5.0 5.0 5.0 5.0 C ns ns ns ns ns ns ns ns input hold time, using iff (with delay) t ph (min) xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C ns ns ns ns ns ns ns ns off = output flip-flop, iff = input flip-flop or latch off global clock-to-output delay . . . . . x3202 t pg off global clock-to-output delay . . . . . x3202 t pg iff d x3201 input set - up & hold time t pg iff d x3201 input set - up & hold time t pg iff d x3201 input set - up & hold time t pg iff d x3201 input set - up & hold time t pg
r february 11, 2000 (version 1.8) 6-113 xc4000e and xc4000x series field programmable gate arrays 6 xc4000e iob input switching characteristic guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). listed below are representative values for typical pin locations and normal clock loading. for more speci?c, more precise, and worst-case guaranteed data, re?ecting the actual routing structure, use the values provided by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. values apply to all xc4000e devices unless otherwise noted. speed grade -4 -3 -2 -1 units description symbol device min max min max min max min max propagation delays (ttl inputs) pad to i1, i2 pad to i1, i2 via transparent latch, no delay with delay t pid t pli t pdli all devices all devices xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 3.0 4.8 10.4 10.8 10.8 10.8 11.0 11.4 13.8 13.8 2.5 3.6 9.3 9.6 10.2 10.6 10.8 11.2 12.4 13.7 2.0 3.6 6.9 7.4 8.1 8.2 8.3 9.8 11.5 12.4 1.4 2.8 6.4 6.5 6.9 7.0 7.3 8.4 9.0 C ns ns ns ns ns ns ns ns ns ns propagation delays (cmos inputs) pad to i1, i2 pad to i1, i2 via transparent latch, no delay with delay t pidc t plic t pdlic all devices all devices xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 5.5 8.8 16.5 16.5 16.8 17.3 17.5 18.0 20.8 20.8 4.1 6.8 12.4 13.2 13.4 13.8 14.0 14.4 15.6 15.6 3.7 6.2 11.0 11.9 12.1 12.4 12.6 13.0 14.0 14.0 1.9 3.3 6.9 7.0 7.4 7.4 7.8 9.0 9.5 C ns ns ns ns ns ns ns ns ns ns propagation delays clock (ik) to i1, i2 (flip-flop) clock (ik) to i1, i2 (latch enable, active low) t ikri t ikli all devices all devices 5.6 6.2 2.8 4.0 2.8 3.9 2.7 3.2 ns ns hold times (note 1) pad to clock (ik), no delay with delay clock enable (ec) to clock (ik), no delay with delay t ikpi t ikpid t ikec t ikecd all devices all devices all devices all devices 0 0 1.5 0 0 0 1.5 0 0 0 0.9 0 0 0 0 0 ns ns ns ns note 1: input pad setup and hold times are speci?ed with respect to the internal clock (ik). for setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the guaranteed input and output parameters table. note 2: voltage levels of unused pads, bonded or unbonded, must be valid logic levels. each can be con?gured with the internal pull-up (default) or pull-down resistor, or con?gured as a driven output, or can be driven from an external source.
r xc4000e and xc4000x series field programmable gate arrays 6-114 february 11, 2000 (version 1.8) xc4000e iob input switching characteristic guidelines (continued) speed grade -4 -3 -2 -1 units description symbol device min max min max min max min max setup times (ttl inputs) pad to clock (ik), no delay with delay t pick t pickd all devices xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 4.0 10.9 10.9 10.9 11.1 11.3 11.8 14.0 14.0 2.6 8.2 8.7 9.2 9.6 9.8 10.2 11.4 11.4 2.0 6.0 6.1 6.2 6.3 6.4 7.9 9.4 10.0 1.5 4.8 5.1 5.8 5.8 6.0 7.6 8.2 C ns ns ns ns ns ns ns ns ns setup time (cmos inputs) pad to clock (ik), no delay with delay t pickc t pickdc all devices xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 6.0 12.0 12.0 12.3 12.8 13.0 13.5 16.0 16.0 3.3 8.8 9.7 9.9 10.3 10.5 10.9 12.1 12.1 2.4 6.9 8.0 8.1 8.2 8.3 10.0 12.1 12.1 2.4 5.3 5.6 6.3 6.3 6.5 7.9 8.1 C ns ns ns ns ns ns ns ns ns (ttl or cmos) clock enable (ec) to clock (ik), no delay with delay t ecik t ecikd all devices xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 3.5 10.4 10.4 10.4 10.4 10.7 11.1 14.0 14.0 2.5 8.1 8.5 9.1 9.5 9.7 10.1 11.3 11.3 2.1 4.3 5.6 6.7 6.9 7.1 9.0 10.6 11.0 1.5 4.3 5.0 6.0 6.0 6.5 8.0 9.0 C ns ns ns ns ns ns ns ns ns global set/reset (note 3) delay from gsr net through q to i1, i2 gsr width gsr inactive to first active clock (ik) edge t rri t mrw t mri 13.0 12.0 11.5 7.8 11.5 6.8 10.0 6.8 ns ns note 1: input pad setup and hold times are speci?ed with respect to the internal clock (ik). for setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the guaranteed input and output parameters table. note 2: voltage levels of unused pads, bonded or unbonded, must be valid logic levels. each can be con?gured with the internal pull-up (default) or pull-down resistor, or con?gured as a driven output, or can be driven from an external source. note 3: timing is based on the xc4005e. for other devices see the xact timing calculator.
r february 11, 2000 (version 1.8) 6-115 xc4000e and xc4000x series field programmable gate arrays 6 xc4000e iob output switching characteristic guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more speci?c, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature). values apply to all xc4000e devices unless otherwise noted. speed grade -4 -3 -2 -1 units description symbol min max min max min max min max propagation delays (ttl output levels) clock (ok) to pad, fast slew-rate limited output (o) to pad, fast slew-rate limited 3-state to pad hi-z (slew-rate independent) 3-state to pad active and valid, fast slew-rate limited t okpof t okpos t opf t ops t tshz t tsonf t tsons 7.5 11.5 8.0 12.0 5.0 9.7 13.7 6.5 9.5 5.5 8.5 4.2 8.1 11.1 4.5 7.0 4.8 7.3 3.8 7.3 9.8 3.0 5.0 3.2 5.2 3.0 6.8 8.8 ns ns ns ns ns ns ns propagation delays (cmos output levels) clock (ok) to pad, fast slew-rate limited output (o) to pad, fast slew-rate limited 3-state to pad hi-z (slew-rate independent) 3-state to pad active and valid, fast slew-rate limited t okpofc t okposc t opfc t opsc t tshzc t tsonfc t tsonsc 9.5 13.5 10.0 14.0 5.2 9.1 13.1 7.8 11.6 9.7 13.4 4.3 7.6 11.4 7.0 10.4 8.7 12.1 3.9 6.8 10.2 4.0 7.0 4.0 6.0 3.9 6.8 8.8 ns ns ns ns ns ns ns note 1: output timing is measured at pin threshold, with 50pf external capacitive loads (incl. test ?xture). slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. for the effect of capacitive loads on ground bounce, see the additional xc4000 data section of the programmable logic data book. note 2: voltage levels of unused pads, bonded or unbonded, must be valid logic levels. each can be con?gured with the internal pull-up (default) or pull-down resistor, or con?gured as a driven output, or can be driven from an external source.
r xc4000e and xc4000x series field programmable gate arrays 6-116 february 11, 2000 (version 1.8) iob output switching characteristics guidelines (continued) speed grade -4 -3 -2 -1 units description symbol min max min max min max min max setup and hold output (o) to clock (ok) setup time output (o) to clock (ok) hold time clock enable (ec) to clock (ok) setup clock enable (ec) to clock (ok) hold t ook t oko t ecok t okec 5.0 0 4.8 1.2 4.6 0 3.5 1.2 3.8 0 2.7 0.5 2.3 0 2.0 0 ns ns ns ns clock clock high clock low t ch t cl 4.5 4.5 4.0 4.0 4.0 4.0 3.0 3.0 ns ns global set/reset (note 3) delay from gsr net to pad gsr width gsr inactive to first active clock (ok) edge t rpo t mrw t mro 13.0 15.0 11.5 11.8 11.5 8.7 7.0 ns ns note 1: output timing is measured at pin threshold, with 50pf external capacitive loads (incl. test ?xture). slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. for the effect of capacitive loads on ground bounce, see the additional xc4000 data section of the programmable logic data book. note 2: voltage levels of unused pads, bonded or unbonded, must be valid logic levels. each can be con?gured with the internal pull-up (default) or pull-down resistor, or con?gured as a driven output, or can be driven from an external source. note 3: timing is based on the xc4005e. for other devices see the xact timing calculator.
r february 11, 2000 (version 1.8) 6-117 xc4000e and xc4000x series field programmable gate arrays 6 xc4000e boundary scan (jtag) switching characteristic guidelines testing of the switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are not measured directly. they are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. for more detailed, more precise, and more up-to-date information, use the values provided by the xact timing calculator and used in the simulator. these values can be printed in tabular format by running lca2xnf -s. the following guidelines re?ect worst-case values over the recommended operating conditions. they are expressed in units of nanoseconds and apply to all xc4000e devices unless otherwise noted. revision control speed grade -4 -3 -2 -1 units description symbol min max min max min max min max setup times input (tdi) to clock (tck) input (tms) to clock (tck) t tditck t tmstck 30.0 15.0 30.0 15.0 30.0 15.0 20.0 10.0 ns ns hold times input (tdi) to clock (tck) input (tms) to clock (tck) t tcktdi t tcktms 0 0 0 0 0 0 0 0 ns ns propagation delay clock (tck) to pad (tdo) t tckpo 30.0 30.0 30.0 20.0 ns clock clock (tck) high clock (tck) low t tckh t tckl 5.0 5.0 5.0 5.0 5.0 5.0 4.0 4.0 ns ns frequency f max 15.0 15.0 15.0 25.0 mhz note 1: input setup and hold times and clock-to-pad times are speci?ed with respect to external signal pins. note 2: output timing is measured at pin threshold, with 50pf external capacitive loads (incl. test ?xture). slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. for the effect of capacitive loads on ground bounce, see the additional xc4000 data section of the programmable logic data book. note 3: voltage levels of unused pads, bonded or unbonded, must be valid logic levels. each can be con?gured with the internal pull-up (default) or pull-down resistor, or con?gured as a driven output, or can be driven from an external source. version nature of changes 3/30/98 (1.5) as submitted for the 1999 data book 1/29/99 (1.5) updated switching characteristics tables 5/14/99 (1.6) replaced electrical specification and pinout pages for e, ex, and xl families with separate updates and added url link on placeholder page for electrical specifications/pinouts for weblinx users 8/27/99 (1.7) included missing iob propagation delay page (6-113) 2/11/00 (1.8) altered iob heads (acrobat pdf file problem), corrected dual-port write mins for -4 speed grade.

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